The present invention relates to a MOS transistor output circuit. CMOS inverters have been heretofore used as output circuits of semiconductor integrated circuits of CMOS configuration. In such a configuration, if a large capacitive load exists at the output terminal, or if a number of output circuits operate simultaneously, noises such as ringing and ground bounces present problems. Ringing noises in an output circuit are caused by the fact that a rapid switching current due to rising and falling edges of signal flows through a resonant circuit consisting of an L-component, output transistors, and capacitive loads. The L-component is due to bonding wires at the output terminal. The ground bounces are caused by a counter electromotive force induced by flow of the aforementioned switching current through bonding wires at the power-supply terminals.
One conventional countermeasure against these noises is to use a method consisting of dividing output transistors in parallel and turning them on in turn to alleviate the rapid increase of the switching current. This configuration is shown in FIG. 6, where a CMOS inverter consisting of a p-channel MOS transistor 61 and an n-channel MOS transistor 62 has an output terminal OUT. These transistors 61 and 62 act as output transistors. There are other output transistors 63 and 64 whose drains are connected with the output terminal OUT of the CMOS inverter. The transistor 63 is a p-channel MOS transistor, while the transistor 64 is an n-channel MOS transistor. Thus, the p-channel output transistors are divided into the MOS transistors 61 and 63. The n-channel output transistors are divided into the MOS transistors 62 and 64. Signals applied to the gates of the p-channel MOS transistor 61 and n-channel MOS transistor 62 are delayed by delay circuits 65 and 66, respectively, and supplied to the gates of the MOS transistors 63 and 66, respectively. The p-channel MOS transistor 63 and n-channel transistor 64 are turned on and off in a delayed manner compared with the MOS transistors 61 and 62.
In another available method, the output transistors are divided in parallel, and the output transistors are turned off in a stepwise fashion according to the state of the output. This reduces rapid decrease of the switching current. A configuration implementing this method is constructed as shown in FIG. 7, where a CMOS inverter has output transistors 71 and 72. The transistor 71 consists of a p-channel MOS transistor, while the transistor 72 consists of an n-channel MOS transistor. The CMOS inverter further includes output transistors 73 and 74 whose drains are connected with the output terminal OUT of the CMOS transistor. The transistor 73 is a p-channel MOS transistor, whereas the transistor 74 is an n-channel MOS transistor. The MOS transistors 73 and 74 are connected with power-supply terminals VDD and VSS, respectively, via a p-channel MOS transistor 75 and an n-channel MOS transistor 76, respectively. The gates of the MOS transistors 75 and 76 are connected with the output terminal. The MOS transistors 73 and 74 are turned on simultaneously with the MOS transistors 71 and 72, respectively. This inverts the output signal. In response to this, the MOS transistors 75 and 76 are turned off. As a result, the MOS transistors 73 and 74 are cut off.
One configuration in which output transistors are divided in parallel and turned off in a stepwise fashion according to the state of the output is described in Japanese Unexamined Patent Publication No. 249974/1995 and shown in FIG. 8. This circuitry includes output transistors P1, P2, N1, N2, as well as p-channel MOS transistors P3-P7 and n-channel MOS transistors N3-N7 for controlling signals applied to the gates of the output transistors P1, P2, N1, and N2 in response to the state at the output terminal C. The transistors P1 and P2 are p-channel MOS transistors, while the transistors N1 and N2 are n-channel MOS transistors. Where the MOS transistors P1 and N1 have a large size, the MOS transistors P3, N3, P4, and N4 have a medium size, the MOS transistors P2, N2, P5, and N5 have a small size, and the MOS transistors P6, N6, P7, and N7 have a very small size.
The prior art methods, although useful in reducing ringing noises and ground bounces in out put circuits, are inefficient or undesirable for one or more of the following reasons. For example, in the configuration shown in FIG. 6, the output transistors divided in parallel are turned on and off in a stepwise manner. Therefore, the rising and fall speeds of the output signal are deteriorated. Hence, this configuration is not adapted for circuits to be operated at high speeds.
On the other hand, in the configuration shown in FIG. 7 the divided output transistors are turned on without time difference and so it is said that neither the rising speed nor the falling speed of the output signal decreases. In practice, however, the switching MOS transistors 75 and 76 used for feedback to the output transistors must be added in series. The resistive components of the added transistors decrease the rising and falling speeds of the output signal. Consequently, the configuration does not function efficiently especially at low power-supply voltages.
In the configuration shown in FIG. 8, a signal is fed back to the MOS transistor P1 from the output terminal C via the MOS transistors N4 and P6. The MOS transistor N4 is connected in series with the MOS transistor N3, forming a composite gate. If MOS transistors are connected in series, the threshold value of the MOS transistor N4 is increased by the substrate-bias effect. This reduces the capability of driving the following stage. To compensate for this, the size of the transistors must be increased. The feedback to the MOS transistor P2 from the output terminal C is now compared with the case of the MOS transistor P1. Since the positions of the p-channel and n-channel transistors have been interchanged, the driving ability is lowered further. When the MOS transistor N3 turns on, the state of the output signal from the output terminal C varies. Thus, the MOS transistors N4 and P5 are making a transition from ON to OFF or vice versa. This means that the MOS transistors N4 and P5 are in a state of low driving ability. Hence, sufficient use of the driving ability of the previous stage of MOS transistor N3 cannot be made. This makes it difficult to operate the final stage of MOS transistors P1 and P2 at high speeds. Therefore, the size needs to be increased further to secure the necessary driving ability. In the same way as the configuration shown in FIG. 7, the driving ability becomes insufficient, especially when the power-supply voltage is low. In this way, this configuration is not a practically effective means.
Accordingly, it is an object of the present invention to provide a MOS transistor output circuit that has no feedback portion in its output stage and is capable of operating at high speed under lower power-supply voltages.
In a MOS transistor output circuit in accordance with the present invention, two output transistors are provided for the p-channel side and two output transistors are provided for the n-channel side. Thus, the output transistors are divided. A signal corresponding to an input signal is applied to the gates of the first p-channel MOS transistor and the first n-channel MOS transistor. The rising edge and the falling edge of the input signal are detected to produce first and second signals. These first and second signals are applied to the gates of the second p-channel MOS transistor and the second n-channel MOS transistor, respectively, thus turning off the output transistors in turn. This suppresses noises such as ringing and ground bounces. Because of this configuration, the output section has no feedback portion. As a result, the MOS transistor output circuit can operate at higher speeds under lower power-supply voltages.
In one embodiment of the invention, the drain of the first p-channel MOS transistor is connected with the drain of the first n-channel MOS transistor to form an output terminal. The drains of the second p-channel MOS transistor and the second n-channel MOS transistor are connected to the output terminal described above. A certain signal such as an input signal or a signal corresponding to the inversion of the input signal is applied to the gates of the first p-channel MOS transistor and the first n-channel MOS transistor. For example, if the certain signal corresponds to the input signal, then the falling edge of the input signal is detected to generate the first signal, and the rising edge of the input signal is detected to generate the second signal. If the certain signal corresponds to the inverted signal, then the rising edge of the input signal is detected to generate the first signal and the falling edge of the input signal is detected to generate the second signal.
In operation, the first signal is applied to the gate of the second p-channel MOS transistor. A period starting with the rising edge of the output signal from the output terminal described above and ending when the logic level of the output signal can be regarded as high (H) is herein referred to as a first period. During this first period, the second p-channel MOS transistor is made to conduct. The second signal is applied to the gate of the second n-channel MOS transistor. A period starting with the falling edge of the output signal and ending when the logic level of the output signal can be regarded as low (L) is herein referred as a second period. During this second period, the second n-channel MOS transistor is made to conduct.
Preferably, the delay of the certain signal with respect to the input signal is made substantially equal to the delay of the first and second signals with respect to the rising or falling edge of the input signal.
Other objects and features of the invention will appear in the course of the description thereof, which follows.